1. Field of the Invention
The present invention relates to a conditional keeper and an architecture implementing its application to match lines, particularly to an XOR-based conditional keeper and an architecture implementing its application to match lines.
2. Description of the Related Art
The Internet is formed of networks interconnected with connection nodes, which are usually routers, and data is transmitted there inside according to a common convention, i.e. the Internet protocol. A special memory CAM (Content Addressable Memory) is used to implement rapid and massive parallel searches in the data transmission process of the Internet. During a searching process, CAM compares key words with all data to obtain the target data address, and it is usually pipelined to accelerate search. As search can be initiated at every cycle, the operation rate up to once per cycle can be achieved. Usually, searching speed closely correlates with power consumption. In fact, the power consumption of a sophisticated CAM is generally proportional to its searching speed. Therefore, for maintaining a high-speed data transmission process in the Internet, it is critical to have a circuit design of efficient power management. In conventional technologies, the keeper in the dynamic mach line architecture is used to manage power, determine operation speed and provide anti-noise function. Owing to that IP has been promoted from IPv4 to IPv6, the maximum bit field to be compared also increases from a 32-bit one to a 128-bit one, and the power consumption of the entire match-line circuit also grows. Upsizing the keeper can often enhance noise immunity; however, it also brings about the problems of operation delay and power consumption rise.
The conventional dynamic match line architecture and the keeper design are to be further analyzed below in cooperation with the drawings. The conventional match line architectures can be classified into NOR-type ones and AND-type ones, and the conventional keepers can be classified into feedback ones and weak ones.
Firstly, the conventional match-line technologies are to be introduced. Refer to FIG. 1(a) and FIG. 1(b), wherein FIG. 1(a) is a diagram schematically showing the partial match-line circuit architecture usually seen in a NOR-type CAM, and FIG. 1(b) is a diagram schematically showing the circuit of a single NOR-type CAM cell. The NOR-type match-line architecture shown in FIG. 1(a) is composed of a NOR-type CAM cell set 11, which is formed of NOR-type CAM cells 111 interconnected in series, a transistor switch 13 and an inverter 15, wherein an NOR-type CAM 112 is coupled to the source of a pull-down NMOS (Ndn) 113 to form a NOR-type CAM cell 111.
As shown in FIG. 1(b), the NOR-type CAM is formed via coupling four NMOS's 171, 172, 173, 174 and two inverters 191, 192, and then, the NOR-type CAM is coupled the gate and the source of a pull-down NMOS 175 to form a single NOR-type CAM cell.
Refer to FIG. 2(a) and FIG. 2(b), wherein FIG. 2(a) is a diagram schematically showing the AND-type match-line architecture, and FIG. 2(b) is a diagram schematically showing the circuit of a single AND-type CAM cell.
The AND-type match-line architecture shown in FIG. 2(a) is composed of an AND-type CAM cell set 20, a transistor switch 22 and an inverter 24, wherein an AND-type CAM 202 is coupled to the source of a pull-down NMOS 203 to form a AND-type CAM cell 201. Similarly, as shown in FIG. 2(b), a single AND-type CAM is also formed via coupling four NMOS's 211, 212, 213, 214 and two inverters 231, 232, but the AND-type CAM is coupled to only the gate of a pull-down NMOS 215 to form a single AND-type CAM cell.
After the description of two primary conventional match-line architectures, the conventional keeper architectures are to be introduced below. It is well known: in conventional technologies, what both the NOR-type and AND-type match lines use are general feedback keepers or general weak keepers. Refer to FIG. 3(a) and FIG. 3(b) respectively schematically showing the circuit architectures of the NOR-type match line together with a feedback keeper or a weak keeper. As shown in FIG. 3(a), the match line is formed via coupling a NOR-type CAM cell set 30, wherein NOR-type CAM cells are interconnected in series, to a transistor switch 32; a feedback keeper 34, which is formed of a PMOS, is coupled to the end of the circuit, and lastly, an inverter 36 is further coupled thereto. As shown in FIG. 3(b), the match line is formed via coupling a NOR-type CAM cell set 31, wherein NOR-type CAM cells are interconnected in series, to a transistor switch 33; a weak keeper 35, which is formed via coupling two PMOS's 351, 352, is coupled to the end of the circuit, and lastly, an inverter 37 is further coupled thereto.
In the AND-type match-line architecture, in addition to the feedback keeper and the weak keeper, a dual NMOS design, which can replace the keeper, may also be used. Refer to FIG. 4(a), FIG. 4(b) and FIG. 4(c) respectively schematically showing the circuit architectures of the NOR-type match line together with a feedback keeper, a weak keeper or a dual NMOS. As shown in FIG. 4(a), the match line is formed via coupling an AND-type CAM cell set 400, wherein AND-type CAM cells are interconnected in series, to a transistor switch 402; a feedback keeper 404, which is formed of a PMOS, is coupled to the end of the circuit, and lastly, an inverter 406 is further coupled thereto. As shown in FIG. 4(b), the match line is formed via coupling a AND-type CAM cell set 410, wherein AND-type CAM cells are interconnected in series, to a transistor switch 412; a weak keeper 41, which is formed via coupling two PMOS's 411, 412, is coupled to the end of the circuit, and lastly, an inverter 416 is further coupled thereto. As shown in FIG. 4(c), the match line is also formed via coupling a AND-type CAM cell set 420, wherein AND-type CAM cells are interconnected in series, to a transistor switch 422, but herein, a dual NMOS's 424 is coupled to the end of the circuit to replace the conventional keeper, and lastly, an inverter 426 is further coupled thereto. Nevertheless, none of the feedback keeper in FIG. 4(a), the weak keeper in FIG. 4(b) and the dual NMOS's in FIG. 4(c) can receive a clock signal synchronous with the original CAM cell set; therefore, propagation delay and extra power consumption will appear. In the evaluation phase, if the stored data does not match the searched data, the pull-down NMOS will discharge the floating node to the ground voltage level theoretically. When the pull-down NMOS cannot effectively discharge the floating node to the ground voltage level, the keeper and the pull-down NMOS will turn on simultaneously; however, it will cause strong direct current and intense noise; besides, the feedback path of the conventional keeper will further worsen propagation delay.
When the match-line architectures, which the abovementioned conventional keepers apply to, intend to achieve a given noise immunity, they have to confront the problems of propagation delay and high power consumption. Accordingly, the present invention proposes an XOR-based conditional keeper and an architecture implementing its application to match lines to overcome the abovementioned problems and obtain an optimal compromise among high noise immunity, high processing speed and low power consumption.